1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which is capable of shifting data by connecting bit lines, and a method of shifting data thereof.
2. Description of the Related Art
The capacity of data needed to perform functions is increasing. Data with high correlation among a large amount of data is stored at adjacent addresses in a semiconductor memory device.
In this case, if data at an arbitrary row address can be shifted to a different address, various advantages can be obtained.
FIG. 1 is a view for explaining a conventional operation of shifting data at an arbitrary row address to a different row address.
Referring to FIG. 1, data stored in memory cells connected to a word line WL1 is shifted to memory cells connected to a word line WL2. Such data shifting is useful in shifting the location of a large amount of data in graphic memories, etc. Also, data shifting can be used to selectively refresh only regions in which desired data is stored after the data is stored at adjacent addresses of a memory device.
In addition, if data at an arbitrary row address can be shifted to a different row address, various advantages can be obtained in view of the operation of a memory device.
FIG. 2A is a view illustrating memory cell blocks and sense amplifier blocks of a conventional semiconductor memory device.
FIG. 2A illustrates memory cell blocks MCB1 and MCB2 disposed between the sense amplifier blocks SAB1, SAB2, and SAB3. Each of the sense amplifier blocks SAB1, SAB2, and SAB3 includes a plurality of sense amplifier circuits (not shown).
Bit lines BL of the memory cell block MCB1 are connected to sense amplifier circuits (not shown) of the sense amplifier block SAB2. Inverted bit lines /BL of the memory cell block MCB1 are connected to sense amplifier circuits (not shown) of the sense amplifier block SAB1.
Bit lines BL of the memory cell block MCB2 are connected to sense amplifier circuits (not shown) of the sense amplifier block SAB3. Inverted bit lines /BL of the memory cell block MCB2 are connected to sense amplifier circuits (not shown) of the sense amplifier block SAB2.
FIG. 2B is a schematic view for explaining a connection relationship between sense amplifier circuits included in the sense amplifier blocks and bit lines of FIG. 2A.
Hereinafter, the connection relationship between the bit lines BL, the inverted bit lines /BL, and the sense amplifier circuits SA1, SA2, SA3, and SA4 will be described in more detail with reference to FIG. 2B.
In FIG. 2B, it is assumed that a sense amplifier circuit SA1 is disposed in the sense amplifier block SAB1, a sense amplifier circuit SA2 is disposed in the sense amplifier block SAB2, a sense amplifier circuit SA3 is disposed in the sense amplifier block SAB3, and a sense amplifier circuit SA4 is disposed in another sense amplifier circuit (not shown).
A bit line and an inverted bit line of the same memory cell block are connected to different sense amplifier circuits respectively. That is, a bit line of a first memory cell block and an inverted bit line of a second memory cell block are connected to the same sense amplifier circuit.
Referring to FIG. 2B, a bit line BL and an inverted bit line /BL of the memory cell block MCB1 are connected to a sense amplifier circuit SA2 and a sense amplifier circuit SA1 respectively. That is, a bit line BL of the memory cell block MCB1 and an inverted bit line /BL of the memory cell block MCB2 are connected to the same sense amplifier circuit SA2.
Likewise, a bit line BL of the memory cell block MCB2 and an inverted bit line /BL of the memory cell block MCB3 are connected to the sense amplifier circuit SA3. The configuration described above is called an “open-type” sense amplifier circuit.
FIG. 3A is a view illustrating memory cell blocks and sense amplifier blocks of a conventional semiconductor memory device.
FIG. 3A illustrates memory cell blocks MCB1 and MCB2 disposed between sense amplifier blocks SAB1, SAB2, and SAB3. Each of the sense amplifier blocks SAB1, SAB2, and SAB3 includes a plurality of sense amplifier circuits (not shown).
Bit lines BL and inverted bit lines /BL of the memory cell block MCB1 are alternately connected in pairs to sense amplifier circuits (not shown) of the sense amplifier block SAB2 and to sense amplifier circuits (not shown) of the sense amplifier block SAB1. Also, bit lines BL and inverted bit lines /BL of the memory cell block MCB2 are alternately connected in pairs to sense amplifier circuits (not shown) of the sense amplifier block SAB2 and to sense amplifier circuits (not shown) of the sense amplifier block SAB3.
FIG. 3B is a schematic view for explaining a connection relationship between sense amplifier circuits included in the sense amplifier blocks and bit lines of FIG. 3A. Hereinafter, a connection relationship of the bit lines BL, the inverted bit lines /BL, and the sense amplifier circuit SA1 will be described in more detail with reference to FIG. 3B.
In FIG. 3B, it is assumed that a sense amplifier circuit SA1 is disposed in the sense amplifier block SAB2. A bit line BL and an inverted bit line /BL (bit line pair) of the same memory cell block are connected to the same sense amplifier circuit SA1. In more detail, a bit line BL and an inverted bit line /BL of the memory cell block MCB1 are connected to the sense amplifier circuit SA1. Also, a bit line BL and an inverted bit line /BL of the memory cell block MCB2 are connected to the sense amplifier circuit SA1.
When the bit line BL and inverted bit line /BL of the memory cell block MCB1 are connected to the sense amplifier circuit SA1, isolation transistors ITR1 and ITR2 are turned on in response to a control signal S1, and isolation transistors ITR3 and ITR4 are turned off in response to another control signal S2. Accordingly, when the sense amplifier circuit SA1 operates, the bit line pairs of the memory cell block MCB1 positioned on the one side of the sense amplifier circuit SA1 are connected to the sense amplifier circuits SA1 by the isolation transistors ITR1 and ITR2. And the bit line pairs of the memory cell block MCB2 positioned on the other side of the sense amplifier circuit SA1 are disconnected from the sense amplifier circuits SA1l by the isolation transistors ITR3 and ITR4.
The connection configuration described above is called a “folded-type” sense amplifier circuit.
Conventionally, as illustrated in FIGS. 2A and 3A, bit line pairs of memory cell blocks are isolated from bit line pairs of different memory cell blocks adjacent to the memory cell blocks. However, if bit line pairs of adjacent memory cell blocks are connected to each other, data at an arbitrary row address can be easily shifted to a different row address.